1. Field of the Invention
The present invention relates to semiconductor memories, and in particular to a circuit and modified bits for minimizing the data transfer from a cache memory during a cache miss.
2. Art Background
It is quite common in the computer industry to enhance the speed of the processor in achieving higher over-all performance of a computer system. Recently, wider data bus has been used to improve the transfer of data between semiconductor memories and high-speed processors. Following this trend, designers of high performance computer systems have incorporated instruction pipelines into the architecture of the processors. More recently, caches have been used to further reduce the amount of time a processor takes to retrieve the data or instructions from external memory. A cache is a small but fast memory that stores the most frequently used data or instructions of a computer system. In general, the processor is able to retrieve data from the cache about 80 to 90% (cache hit) without fetching the same from the slower external memory. If a data is not found on the cache (cache miss), the processor will retrieve the data from the slower external memory.
Notwithstanding advances in the various techniques to improve the speed of a processor, the growing bus traffic is becoming the bottleneck in high performance computer systems. To reduce the bus traffic is therefore a key to improving the overall performance of a high speed computer system.
During a cache miss, blocks of data from the cache are transferred out of the cache and written with the needed data blocks from the external memory. A block of data from a data cache consists of at least a line of data. Because a line of data may further comprise at least 16 bytes or up to 64 bytes of data, the reading and writing of such blocks of data contribute to the bus traffic.
It is therefore an object of the present invention to minimize the data transfer from a cache memory during a cache miss.
It is another object of the present invention to transfer a fraction of a block of data from a cache memory during a cache miss.
It is yet another object of the present invention to transfer a fraction of the data block from a cache memory during a cache miss while minimizing the hardware overhead.